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MOSEL VITELIC
V53C16126H HIGH PERFORMANCE 128K X 16 BIT FAST PAGE MODE CMOS DYNAMIC RAM
HIGH PERFORMANCE
Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Fast Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
30
30 ns 16 ns 19 ns 65 ns
35
35 ns 18 ns 21 ns 70 ns
40
40 ns 20 ns 23 ns 75 ns
45
45 ns 22 ns 25 ns 80 ns
50
50 ns 24 ns 28 ns 90 ns
Features
s 128K x 16-bit organization s Fast Page Mode for a sustained data rate of 53 MHz s RAS access time: 30, 35, 40, 45, 50ns s Dual CAS Inputs s Low Power Dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh s Refresh Interval: 512 cycles/8 ms s Available in 40-pin 400 mil SOJ and 40/44L-pin 400 mil TSOP-II packages s Single +5V10% Power Supply s TTL Interface
Description
The V53C16126H is a 131,072 x 16 bit high performance CMOS dynamic random access memory. The V53C16126H offers Fast Page mode with dual CAS inputs. The V53C16126H has asymmetric address, 9-bit row and 8-bit column. All inputs are TTL compatible. Fast Page Mode operation allows random access up to 256 x 16 bits, within a page, with cycle times as short as 19ns. The V53C16126H is ideally suited for a wide variety of high performance computer systems and peripheral applications.
Device Usage Chart
Operating Temperature Range
0C to 70C
Package Outline K
*
Access Time (ns) 30
*
Power 50
*
T
*
35
*
40
*
45
*
Std.
*
Temperature Mark
Blank
V53C16126H Rev. 1.3 February 1998
1
MOSEL VITELIC
V 5 3 C 16 1 2 6 H
V53C16126H
FAMILY
DEVICE
PKG
SPEED ( t RAC)
TEMP. PWR. BLANK (0C to 70C) BLANK (NORMAL) 30 35 40 45 50 (30 ns) (35 ns) (40 ns) (45 ns) (50 ns)
Description
SOJ TSOP-II
Pkg.
K T
Pin Count
40 40/44L
K (SOJ) T (TSOP-II)
16126H-01
40-Pin Plastic SOJ PIN CONFIGURATION Top View
Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8 NC NC WE RAS NC A0 A1 A2 A3 Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
16126H-02
40/44L-Pin Plastic TSOP-II PIN CONFIGURATION Top View Pin Names
Vcc I/O1 I/O2 I/O3 I/O4 Vcc I/O5 I/O6 I/O7 I/O8
1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35
Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss
Vss I/O16 I/O15 I/O14 I/O13 Vss I/O12 I/O11 I/O10 I/O9
A0-A8 RAS UCAS
Address Inputs Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable Data Input, Output +5V Supply 0V Supply No Connect
LCAS
NC NC WE RAS NC A0 A1 A2 A3 Vcc
13 14 15 16 17 18 19 20 21 22
32 31 30 29 28 27 26 25 24 23
16126H-03
NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss
WE OE I/O1-I/O16 VCC VSS NC
Absolute Maximum Ratings*
Ambient Temperature Under Bias ................................ -10C to +80C Storage Temperature (plastic) ..... -55C to +125C Voltage Relative to VSS .................-1.0 V to +7.0 V Data Output Current ..................................... 50 mA Power Dissipation .......................................... 1.0 W
*Note: Operation above Absolute Maximum Ratings can adversely affect device reliability.
TA = 25C, VCC = 5 V 10%, VSS = 0 V
Symbol CIN1 CIN2 COUT Parameter Address Input RAS, CAS, WE, OE Data Input/Output Typ. 3 4 5 Max. 4 5 7 Unit pF pF pF
Capacitance*
*Note: Capacitance is sampled and not 100% tested
V53C16126H Rev. 1.3 February 1998
2
MOSEL VITELIC
Block Diagram
128K x 16
OE WE UCAS LCAS RAS
V53C16126H
RAS CLOCK GENERATOR
CAS CLOCK GENERATOR
WE CLOCK GENERATOR
OE CLOCK GENERATOR
VCC VSS
DATA I/O BUS COLUMN DECODERS
Y0-Y7
I/O 1 I/O2 I/O3
I/O BUFFER
SENSE AMPLIFIERS REFRESH COUNTER
256 x 16 9 A0 A1 * * * A7 A8
I/O4 I/O 5 I/O6 I/O7 I/O8 I/O 9 I/O10 I/O11
ADDRESS BUFFERS AND PREDECODERS
ROW DECODERS
X0- X8
512
MEMORY ARRAY
I/O12 I/O 13 I/O14 I/O15 I/O16
512 x 256 x 16
16126H-04
V53C16126H Rev. 1.3 February 1998
3
MOSEL VITELIC
DC and Operating Characteristics (1-2) TA = 0C to 70C, VCC = 5 V 10%, VSS = 0 V, unless otherwise specified.
Symbol
ILI ILO ICC1
V53C16126H
Parameter
Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) VCC Supply Current, Operating
Access Time
V53C16126H Min.
-10
Typ.
Max.
10
Unit
A A mA
Test Conditions
VSS VIN VCC VSS VOUT VCC RAS, CAS at VIH tRC = tRC (min.)
Notes
-10
10
30 35 40 45 50
200 190 180 170 160 2
1, 2
ICC2 ICC3
VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh 30 35 40 45 50
mA
RAS, CAS at VIH, other inputs VSS tRC = tRC (min.) 2
200 190 180 170 160 190 180 170 160 150 2
mA
ICC4
VCC Supply Current, Fast Page Mode Operation
30 35 40 45 50
mA
Minimum Cycle
1, 2
ICC5
VCC Supply Current, Standby Output Enable other inputs VSS VCC Supply Current, CMOS Standby
mA
RAS = VIH CAS = VIL RAS VCC - 0.2 V, CAS VCC - 0.2 V, All other inputs VSS
1
ICC6
1
mA
VCC VIL VIH VOL VOH
Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
4.5 -1 2.4
5.5 0.8 VCC + 1 0.4
V V V V V IOL = 4.2 mA IOH = -5 mA 3 3
2.4
2.4
V53C16126H Rev. 1.3 February 1998
4
MOSEL VITELIC
AC Characteristics
TA = 0C to 70C, VCC = 5 V 10%, VSS = 0V unless otherwise noted AC Test conditions, input pulse levels 0 to 3V
30 # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol tRAS tRC tRP tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH tRSH (R) tCRP tRCH tRRH tROH tOAC tCAC tRAC tCAA tLZ tHZ tAR tRAD tRSH (W) tCWL tWCS tWCH Parameter RAS Pulse Width Read or Write Cycle Time RAS Precharge Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time RAS Hold Time (Read Cycle) CAS to RAS Precharge Time Read Command Hold Time Referenced to CAS Read Command Hold Time Referenced to RAS RAS Hold Time Referenced to OE Access Time from OE Access Time from CAS Access Time from RAS Access Time from Column Address OE or CAS to Low-Z Output OE or CAS to High-Z Output Column Address Hold Time from RAS RAS to Column Address Delay Time RAS or CAS Hold Time in Write Cycle Write Command to CAS Lead Time Write Command Setup Time Write Command Hold Time 0 0 26 5 35 40 45 50
V53C16126H
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes 30 65 25 30 5 15 0 0 5 0 5 10 5 0 20 75K 35 70 25 35 6 16 0 0 6 0 5 10 5 0 24 75K 40 75 25 40 7 17 0 0 7 0 5 10 5 0 28 75K 45 80 25 45 8 18 0 0 8 0 6 10 5 0 32 75K 50 90 30 50 9 19 0 0 9 0 7 10 5 0 36 75K ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 4
15
0
0
0
0
0
ns
5
16
6
7
8
9
10
ns
17 18 19 20
10 10 30 16
11 11 35 18
12 12 40 20
13 13 45 22
14 14 50 24
ns ns ns ns
12 6,7,14 6, 8, 9 6,7,10
21 22 23
0 0 28 6
0 0 30 6
0 0 35 7
0 0 40 8
ns ns ns
16 16
24
10
14
11
17
12
20
13
23
14
26
ns
11
25
10
10
10
10
10
ns
26
10
11
12
13
14
ns
27 28
0 5
0 5
0 5
0 6
0 7
ns ns
12, 13
V53C16126H Rev. 1.3 February 1998
5
MOSEL VITELIC
AC Characteristics (Cont'd)
30 # 29 30 Symbol tWP tWCR tRWL tDS tDH tWOH tOED tRWC tRRW tCWD tRWD tCRW tAWD tPC tCP tCAR tCAP tDHR tCSR tRPC tCHR tPCM tT tREF Parameter Write Pulse Width Write Command Hold Time from RAS Write Command to RAS Lead Time Data in Setup Time Data in Hold Time Write to OE Hold Time OE to Data Delay Time Read-Modify-Write Cycle Time Read-Modify-Write Cycle RAS Pulse Width CAS to WE Delay RAS to WE Delay in ReadModify-Write Cycle CAS Pulse Width (RMW) Col. Address to WE Delay Fast Page Mode Read or Write Cycle Time CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge Data in Hold Time Referenced to RAS CAS Setup Time CAS- beforeRAS Refresh RAS to CAS Precharge Time CAS Hold Time CAS-beforeRAS Refresh Fast Page Mode Read-ModifyWrite Cycle Time Transition Time (Rise and Fall) Refresh Interval (512 Cycles) 26 35 40 45 50
V53C16126H
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Notes 5 26 5 28 5 30 6 35 7 40 ns ns
31
10
11
12
13
14
ns
32 33 34 35 36 37
0 5 5 5 100 65
0 5 5 5 105 70
0 5 6 6 110 75
0 6 7 7 115 80
0 7 8 8 130 87
ns ns ns ns ns ns
14 14 14 14
38 39
26 50
28 54
30 58
32 62
34 68
ns ns
12 12
40 41 42
44 32 19
46 35 21
48 38 23
50 41 25
52 42 28
ns ns ns 12
43 44
3 16
4 18
5 20
6 22
7 24
ns ns
45
19
21
23
25
27
ns
7
46
28
30
35
40
ns
47
10
10
10
10
10
ns
48 49
0 7
0 8
0 8
0 10
0 12
ns ns
50
56
58
60
65
70
ns
51 52
1.5
50 8
1.5
50 8
1.5
50 8
1.5
50 8
1.5
50 8
ns ms
15 17
V53C16126H Rev. 1.3 February 1998
6
MOSEL VITELIC
Notes:
V53C16126H
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the output open. 2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two transitions per address cycle in Fast Page Mode. 3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to -1.0 V for a period not to exceed 20 ns. All AC parameters are measured with VIL (min.) VSS and VIH (max.) VCC. 4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA (max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC. 5. Either tRRH or tRCH must be satisified for a Read Cycle to occur. 6. Measured with a load equivalent to one TTL input and 100 pF. 7. Access time is determined by the longest of tCAA, tCAC and tCAP. 8. Assumes that tRAD tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD exceeds tRAD (max.). 9. Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD exceeds tRCD (max.). 10. Assumes that tRAD tRAD (max.). 11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 13. tWCS (min.) must be satisfied in an Early Write Cycle. 14. tDS and tDH are referenced to the latter occurrence of CAS or WE. 15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns. 16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent). 17. An initial 200 s pause and 8 RAS-containing cycles are required when exiting an extended period of bias without clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C16126H Rev. 1.3 February 1998
7
MOSEL VITELIC
Truth Table
Function
Standby Read: Word Read: Lower Byte
V53C16126H
RAS
H L L
LCAS
H L L
UCAS
H L H
WE
X H H
OE
X L L
ADDRESS
X ROW/COL ROW/COL High-Z Data Out
I/O
Notes
Lower Byte, Data-Out Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-Out Data-In Lower Byte, Data-In Upper Byte, High-Z Lower Byte, High-Z Upper Byte, Data-In Data-Out, Data-In Data-Out Data-In Data-Out, Data-In Data-Out High-Z High-Z 3 1,2 2 2 1,2 2
Read: Upper Byte
L
H
L
H
L
ROW/COL
Write: Word (Early-Write) Write: Lower Byte (Early)
L L
L L
L H
L L
X X
ROW/COL ROW/COL
Read: Upper Byte (Early)
L
H
L
L
X
ROW/COL
Read-Write Page-Mode Read Page-Mode Write Page-Mode Read-Write Hidden Refresh Read RAS-Only Refresh CBR Refresh
L L L L LHL L HL
L HL HL HL L H L
L HL HL HL L H L
HL H L HL H X X
LH L X LH L X X
ROW/COL COL COL COL ROW/COL ROW X
Notes:
1. Byte Write cycles LCAS or UCAS active. 2. Byte Read cycles LCAS or UCAS active. 3. Only one of the two CAS must be active (LCAS or UCAS).
V53C16126H Rev. 1.3 February 1998
8
MOSEL VITELIC
Waveforms of Read Cycle
t RC (2) t RAS (1) RAS VIH VIL t CSH (4) t CRP (13) UCAS, LCAS VIH VIL t ASR (8) ADDRESS VIH VIL ROW ADDRESS t RAD (24) t RAH (9) t ASC (10) COLUMN ADDRESS t CAR (44) t RCS (7) WE VIH VIL t CAA (20) OE VIH VIL t CAC (18) t RAC (19) I/O VOH VOL t LZ (21) t HZ (22) VALID DATA-OUT t OAC (17) t ROH (16) t RRH (15) t CAH (11) t RCD (6) t RSH (R)(12) t CAS (5) t AR (23) t RP (3)
V53C16126H
t CRP (13)
t RCH (14)
t HZ (22)
16126H-05
Waveforms of Early Write Cycle
t RC (2) t RAS (1) RAS V IH V IL t CSH (4) t CRP (13) UCAS, LCAS V IH V IL t RAH (9) t ASR (8) ADDRESS V IH V IL ROW ADDRESS t RAD (24) t CWL (26) V IH V IL t WCR (30) t RWL (31) OE V IH V IL t DHR (46) t DS (32) I/O V IH V IL t DH (33) VALID DATA-IN HIGH-Z
16126H-06
t RP (3)
t AR (23)
t RCD (6)
t RSH (W)(25) t CAS (5)
t CRP (13)
t CAR (44) t CAH (11) t ASC (10)
COLUMN ADDRESS t WCH (28) t WP (29) t WCS (27)
WE
Don't Care
V53C16126H Rev. 1.3 February 1998
Undefined
9
MOSEL VITELIC
Waveforms of OE-Controlled Write Cycle
t RC (2) t RAS (1) RAS VIH V IL t CRP (13) V IH UCAS, LCAS V IL t RAD (24) t RAH (9) t ASR (8) ADDRESS V IH V IL ROW ADDRESS t CAR (44) t CAH (11) t ASC (10) COLUMN ADDRESS t CWL (26) t RWL (31) t WP (29) WE V IH V IL t WOH (34) OE V IH V IL t OED (35) V IH V IL t DH (33) t DS (32) VALID DATA-IN t CSH (4) t RCD (6) t RSH (W)(12) t CAS (5) t AR (23) t RP (3)
V53C16126H
t CRP (13)
I/O
16126H-07
Waveforms of Read-Modify-Write Cycle
t RWC (36) tRRW (37) RAS VIH VIL t CSH (4) t CRP (13) VIH UCAS, LCAS VIL t RAH (9) t ASR (8) ADDRESS VIH VIL ROW ADDRESS t RAD (24) t RWD (39) WE VIH VIL VIH VIL t OED (35) t CAC (18) t RAC (19) I/O VIH VOH VIL VOL t LZ (21) VALID DATA-OUT t HZ (22) t DS (32) VALID DATA-IN
16126H-08
t RP (3)
t AR (23)
t RCD (6)
t RSH (W)(25) t CRW (40) t t ASC (10) COLUMN ADDRESS t AWD (41) t CWD (38) t RWL (31) t CWL (26)
t CRP (13)
CAH (11)
t WP (29)
t CAA (20) t OAC (17)
OE
t DH (33)
Don't Care
V53C16126H Rev. 1.3 February 1998
Undefined
10
MOSEL VITELIC
Waveforms of Fast Page Mode Read Cycle
RAS V IH V IL t RCD (6) t CRP (13) UCAS, LCAS V IH V IL t RAH (9) t CSH (4) t ASC (10) t CAH (11) COLUMN ADDRESS t RCH (14) t CAH (11) t CAA (20) t OAC (17) OE V IH V IL t RAC (19) t CAC (18) t LZ (21) t HZ (22) t CAC (18) t HZ (22) t LZ (21) I/O V OH V OL VALID DATA OUT VALID DATA OUT t LZ (21) t CAC (18) t HZ (22) t HZ (22) t RCS (7) t CAR (44) t PC (42) t CP (43) t RSH (R)(12) t CAS (5) t AR (23) t RASP (37)
V53C16126H
t
RP (3)
t CAS (5)
t CRP (13) t CAS (5)
t ASR (8) ADDRESS V IH V IL
t ASC (10) ROW ADDRESS t RCS (7)
t CAH (11) COLUMN ADDRESS t RCS (7) t RCH (14)
COLUMN ADDRESS
WE
V IH V IL t CAP (45) t OAC (17) t CAA (20) t OAC (17) t RRH (15)
t HZ (22) t HZ (22)
VALID DATA OUT
16126H-09
Waveforms of Fast Page Mode Write Cycle
t AR (23) RAS V IH V IL t CRP (13) t RCD (6) UCAS, LCAS V IH V IL t RAH (9) t ASR (8) ADDRESS V IH V IL t RAD (24) t WCS (27) t WP (29) WE V IH V IL VIH V IL t DS (32) I/O V IH V IL
VALID DATA IN ROW ADD COLUMN ADDRESS
t RP (3) t RASP (37)
t PC (42) t CP (43) t CAS (5)
t RSH (W)(25) t CAS (5) t CAS (5)
t CRP (13)
t CSH (4) t ASC (10)
COLUMN ADDRESS
t CAH (11)
t CAH (11)
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS
t CWL (26)
t WCH (28)
t WCS (27)
t CWL (26)
t WCH (28) t WP (29)
t WCS (27)
t CWL (26) t RWL (31) t WCH (28) t WP (29)
OE
t DS (32) t DH (33)
OPEN VALID DATA IN
t DS (32) t DH (33)
VALID DATA IN
t DH (33)
OPEN
16126H-10
Don't Care
V53C16126H Rev. 1.3 February 1998
Undefined
11
MOSEL VITELIC
Waveforms of Fast Page Mode Read-Write Cycle
RAS VIH V
IL
V53C16126H
t RASP (37)
t RCD (6)
t CSH (4) t PCM (50) t CAS (5)
t RP (3) t RSH (W)(25) t CRP (13) t CAS (5)
t CP (43) t CAS (5)
V UCAS, LCAS V
IH IL
t RAD (24) t RAH (9) t ASR (8) t ASC (10) t ASC (10)
COLUMN ADDRESS
t CAH (11)
COLUMN ADDRESS
t CAH (11)
t ASC (10)
t CAR (44) t CAH (11)
COLUMN ADDRESS
V ADDRESS V
IH IL
ROW ADD
t RCS (7) V WE V
IH IL
t RWD (39) t CWD (38)
t CWL (26)
t CWD (38) t CWL (26)
t CWD (38) t RWL (31) t CWL (26)
t CAA (20) t OAC (17) V OE V
IH IL
t AWD (41)
t AWD (41) t WP (29) t OAC (17)
t AWD (41) t OAC (17) t WP (29) t WP (29)
t OED (35) t CAC (18) t RAC (19)
t CAA (20)
t CAP (43)
t OED (35) t CAC (18) t DH (33)
t CAP (43) t CAA (20)
t HZ (22)
t HZ (22)
t DS (32) I/O V I/OH V I/OL t LZ (21)
OUT IN OUT
t DH (33) t DS (32)
t OED (35) t CAC (18) t HZ (22) t DH (33) t DS (32)
OUT IN
IN
t LZ (21)
t LZ (21)
16126H-11
Waveforms of RAS-Only Refresh Cycle
t RC (2) V IH V IL t CRP (13) UCAS, LCAS V IH V IL t ASR (8) ADDRESS V IH V IL NOTE: ROW ADDR
16126H-12
t RAS (1)
t RP (3)
RAS
t RAH (9)
WE, OE = Don't care
Don't Care
V53C16126H Rev. 1.3 February 1998
Undefined
12
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1) RAS V IH V IL t CSR (47) UCAS, LCAS V IH V IL V IH V IL READ V IH V IL t ROH (16) t OAC (17) OE V IH V IL t LZ (21) I/O V IH V IL WRITE V IH V IL V IH V IL t I/O V IH V IL
DS (32)
V53C16126H
t RP (3)
t CHR (49)
t CP (43)
t RSH (W)(25) t CAS (5)
ADDRESS
t RCS (7)
t RRH (15) t RCH (14)
WE
t HZ (22) t HZ (22) D OUT t RWL (31) t CWL (26)
t WCS (27)
t WCH (28)
WE
OE
t DH (33) D IN
16126H-13
Waveforms of CAS-before-RAS Refresh Cycle
t RC (2) t RP (3) RAS VIH VIL t CP (43) t CSR (47) CAS VIH V IL t HZ (22) I/O VOH VOL NOTE: WE, OE, A 0 -A 8 = Don't care
16126H-14
t RAS (1)
t RP (3)
t RPC (48) t CHR (49)
Don't Care
V53C16126H Rev. 1.3 February 1998
Undefined
13
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
t RC (2) V IH V IL t RCD (6) t CRP (13) UCAS, LCAS V IH V IL t ASR (8) t RAH (9) ADDRESS V IH V IL V IH V IL t CAA (20) t OAC (17) OE V IH V IL t CAC (18) t LZ (21) t RAC (19) V OH I/O V OL VALID DATA t HZ (22) t HZ (22)
ROW ADD
V53C16126H
t RC (2) tRP (3) t RAS (1) t RP (3)
t RAS (1) t AR (23)
RAS
t RSH (R)(12)
t CHR (49)
t CRP (13)
t RAD (24) t ASC (10) t CAH (11)
COLUMN ADDRESS
t RCS (7) WE
t RRH (15)
16126H-15
Waveforms of Hidden Refresh Cycle (Write)
t RC (2) V IH RAS V IL t RCD (6) t CRP (13) UCAS, LCAS V IH V IL t ASR (8) t RAH (9) ADDRESS V IH V IL V IH V IL V IH OE V IL t DS (32) V IH I/O V IL t DH (33)
VALID DATA-IN ROW ADD
t RC (2) t RP (3) t RAS (1) t RP (3)
t RAS (1) t AR (23)
t RSH (12)
t CHR (49)
t CRP (13)
t RAD (24) t ASC (10) t CAH (11)
COLUMN ADDRESS
t WCS (27) WE
t WCH (28)
t DHR (46)
16126H-16
Don't Care
V53C16126H Rev. 1.3 February 1998
Undefined
14
MOSEL VITELIC
Functional Description
The V53C16126H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications. It is functionally similar to a traditional dynamic RAM. The V53C16126H reads and writes data by multiplexing an 17-bit address into a 9-bit row and a 8-bit column address. The row address is latched by the Row Address Strobe (RAS). The column address "flows through" an internal address buffer and is latched by the Column Address Strobe (CAS). Because access time is primarily dependent on a valid column address rather than the precise time that the CAS edge occurs, the delay time from RAS to CAS has little effect on the access time.
V53C16126H
whether WE or CAS falls later. Consequently, the input data must be valid at or before the falling edge of WE or CAS, whichever occurs last. In the CAS-controlled Write Cycle, when the leading edge of WE occurs prior to the CAS low transition, the I/O data pins will be in the High-Z state at the beginning of the Write function. Ending the Write with RAS or CAS will maintain the output in the High-Z state. In the WE controlled Write Cycle, OE must be in the high state and tOED must be satisfied.
Refresh Cycle
To retain data, 512 Refresh Cycles are required in each 8 ms period. There are two ways to refresh the memory: 1. By clocking each of the 512 row addresses (A0 through A8) with RAS at least once every 8 ms. Any Read, Write, Read-Modify-Write or RASonly cycle refreshes the addressed row. 2. Using a CAS-before-RAS Refresh Cycle. If CAS makes a transition from low to high to low after the previous cycle and before RAS falls, CASb e f o r e -R A S r e f r e s h i s a c t i v a t e d . T h e V53C8256H uses the output of an internal 9-bit counter as the source of row addresses and ignore external address inputs. CAS-before-RAS is a "refresh-only" mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. A CAS-before-RAS counter test mode is provided to ensure reliable operation of the internal refresh counter.
Memory Cycle
A memory cycle is initiated by bringing RAS low. Any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. This ensures proper device operation and data integrity. A new cycle must not be initiated until the minimum precharge time tRP /t CP has elapsed.
Read Cycle
A Read cycle is performed by holding the Write Enable (WE) signal High during a RAS/CAS operation. The column address must be held for a minimum specified by tAR. Data Out becomes valid only when tOAC , t RAC , t CAA and t CAC are all satisifed. As a result, the access time is dependent on the timing relationships between these parameters. For example, the access time is limited by tCAA when tRAC, tCAC and tOAC are all satisfied.
Write Cycle
A Write Cycle is performed by taking WE and CAS low during a RAS operation. The column address is latched by CAS. The Write Cycle can be WE controlled or CAS controlled depending on
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Fast Page Mode Operation
Fast Page Mode operation permits all 256 columns within a selected row of the device to be randomly accessed at a high data rate. Maintaining RAS low while performing successive CAS cycles retains the row address internally and eliminates the need to reapply it for each cycle. The column address buffer acts as a transparent or flowthrough latch while CAS is high. Thus, access begins from the occurrence of a valid column address rather than from the falling edge of CAS, eliminating tASC and tT from the critical timing path. CAS latches the address into the column address buffer and acts as an output enable. During Fast Page Mode operation, Read, Write, Read-ModifyWrite or Read-Write-Read cycles are possible at random addresses within a row. Following the initial entry cycle into Fast Page Mode, access is tCAA or tCAP controlled. If the column address is valid prior to the rising edge of CAS, the access time is referenced to the CAS rising edge and is specified by tCAP. If the column address is valid after the rising CAS edge, access is timed from the occurrence of a valid address and is specified by tCAA . In both cases, the falling edge of CAS latches the address and enables the output. Fast Page Mode provides sustained data rates up to 53 MHz for applications that require high data rates such as bit-mapped graphics or high-speed signal processing. The following equation can be used to calculate the maximum data rate: 256 Data Rate = ---------------------------------------t RC + 255 x t PC
V53C16126H
also disable the output drivers when CAS is low. During a Write cycle, if WE goes low at a time in relationship to CAS that would normally cause the outputs to be active, it is necessary to use OE to disable the output drivers prior to the WE low transition to allow Data In Setup Time (tDS) to be satisfied.
Power-On
After application of the VCC supply, an initial pause of 200 s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a RAS clock). Eight initialization cycles are required after extended periods of bias without clocks (greater than the Refresh Interval). During Power-On, the VCC current requirement of the V53C16126H is dependent on the input levels of RAS and CAS. If RAS is low during Power-On, the device will go into an active cycle and ID D will exhibit current transients. It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges.
Table 1. V53C16126H Data Output
Operation for Various Cycle Types
Cycle Type
Read Cycles
I/O State
Data from Addressed Memory Cell High-Z
CAS-Controlled Write Cycle (Early Write) WE-Controlled Write Cycle (Late Write) Read-Modify-Write Cycles
Data Output Operation
The V53C16126H Input/Output is controlled by OE, CAS, WE and RAS. A RAS low transition enables the transfer of data to and from the selected row address in the Memory Array. A RAS high transition disables data transfer and latches the output data if the output is enabled. After a memory cycle is initiated with a RAS low transition, a CAS low transition or CAS low level enables the internal I/O path. A CAS high transition or a CAS high level disables the I/O path and the output driver if it is enabled. A CAS low transition while RAS is high has no effect on the I/O data path or on the output drivers. The output drivers, when otherwise enabled, can be disabled by holding OE high. The OE signal has no effect on any data stored in the output latches. A WE low level can
OE Controlled. High OE = High-Z I/Os Data from Addressed Memory Cell Data from Addressed Memory Cell High-Z
Fast Page Mode Read
Fast Page Mode Write Cycle (Early Write) Fast Page Mode Read-ModifyWrite Cycle RAS-only Refresh CAS-before-RAS Refresh Cycle
Data from Addressed Memory Cell High-Z Data remains as in previous cycle High-Z
CAS-only Cycles
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Package Outlines
40-Pin Plastic SOJ
1.025 TYP. (1.035 MAX.) [26.04 TYP. (26.29 MAX.)] 40 21
V53C16126H
Unit in inches [mm]
0.400 0.005 [10.16 0.127]
0.440 0.005 [11.18 0.127]
1
20 0.026 MIN [0.660 MIN] 0.144 MAX [3.66 MAX]
0.010
+ 0.004 - 0.002
+0.004 0.025 -0.002
+0.102 0.635 -0.051
+0.102 0.254 -0.051
0.050 0.006 [1.27 0.152]
0.04 [0.1]
0.018
+0.004 -0.002
+0.102 0.457 -0.051
40/44L-Pin TSOP-II
0.0047 - 0.0083 [0.119 - .211] 40 21 Unit in inches [mm]
0.017 - 0.023 [0.432 - 0.584]
0.462 - 0.470 [11.73 - 11.94]
0.396 - 0.404 [10.06 - 10.26]
1 0.0315 BSC [.8001 BSC] 0.039 - 0.047 [0.991 - 1.193] 0.721 - 0.729 [18.31 - 18.52] 0.012 - 0.016 [0.305 - 0.406]
20 0-5 0.002 - 0.008 [0.051 - 0.203] BASE PLANE SEATING PLANE
V53C16126H Rev. 1.3 February 1998
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0.368 0.010 [9.35 0.254]
MOSEL VITELIC
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V53C16126H
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(c) Copyright 1998, MOSEL VITELIC Inc.
2/98 Printed in U.S.A.
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MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
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